When an integrated circuit is fabricated, interconnects may build up a charge during various process steps. Interconnects generally refer to the wires used to link transistors together and may be fabricated from metal or polysilicon. When an interconnect with a large surface area is connected to the gate of a MOS transistor, the charge accumulated on the interconnect may result in a sufficiently high voltage potential on the gate to rupture the gate oxide. As fabrication process advances continue to shrink feature sizes, the gate oxide thickness of devices also continues to decrease. Thus, MOS transistors fabricated with thinner gate oxide layers become more susceptible to damage caused by charge build-up on a via connected to the gate of the device.
To reduce the likelihood of process induced gate oxide damage due to charge build-up, generally referred to as the “antenna effect,” a design rule checker may be run to flag antenna effects likely to cause gate oxide breakdown. An “antenna” may be any interconnect, i.e., a conductor such as polysilicon or metal, that is in electrical contact with a gate. These exposed polysilicon or metal structures connected to the gate generally collect charge from the processing environment, e.g., reactive ion etch. This charge can be concentrated in the gate oxide resulting in a voltage potential sufficiently large to rupture the gate oxide if an alternative electrical path does not exist to bleed-off the accumulated charge.
During the design process, design verification and layout software generally referred to as design rule checker (DRC) programs are generally used to predict antenna ratios and flag ratios likely to cause the antenna effect. The “antenna ratio” of an interconnect is generally defined as the ratio between the physical area of the conductors making up the antenna to the total gate oxide area to which the antenna is connected. A higher ratio implies a greater propensity for gate oxide failure due to the antenna effect. A higher ratio may be the result of a relatively larger area to collect charge or a reduced gate oxide area on which the charge is concentrated.
FIG. 1 depicts a portion of an integrated circuit 100 fabricated on a p-type substrate 102. The integrated circuit 100 has multiple metal layers M1, M2, M3, M4 and n-type diffusions 104A-104F. A transistor gate 110 is connected to metal layer M3 through vias 106. Metal layer M3 then is connected to a diffusion region 104C through vias 108 and metal layer M4. In this particular situation, the area (length times width) of the metal line may not be large enough to accumulate sufficient charge during fabrication. Therefore, during the design phase, a DRC program would not flag this situation.
Now consider another transistor with a gate 116. The gate 116 is connected to metal layer M3 through vias 112. Again, metal layer M3 eventually connects to a diffusion region 104F through vias 114 and metal layer M4. However, in this case, the area of this interconnect may be large enough due to its increased length to accumulate enough charge to rupture the oxide of gate 116. That is, during processing, a gate oxide may be ruptured by accumulated charge if the gate sees a long metal interconnect before a diffusion region does. In such situations, a DRC program would flag such interconnect regions as antenna rule violations. Generally an interconnect in close enough proximity with a diffusion region is considered safe because the diffusion region will allow the charge accumulated on the interconnect to leak away harmlessly.
One conventional solution to the antenna problem involves adding a diode near a susceptible transistor as depicted in FIG. 2. Diode 200 is connected to gate 202 via metal layer M1. Diode 200 may be fabricated by placing a n diffusion 206 in a p substrate 208 to form a pn junction diode. During normal chip operation, this diode 200 is reverse biased, i.e., turned off and not conducting any current. However, during processing, the diode 200 allows charge to leak away harmlessly should the voltage potential on the gate become greater than the forward voltage, Vf, of the diode 200. When the gate voltage reaches Vf, the diode 200 becomes conducting, allowing current to flow from the gate to the substrate, i.e., the diode 200 bleeds the charge off through the substrate. Thus, if the gate is designed to withstand a voltage potential of about 1 volt, a diode with a forward voltage drop of about 0.7 volt will bleed-off charge before the gate potential reaches 1 volt, providing protection for the transistor device.
However, this approach generally requires the addition of diodes to a chip layout when antenna violations are discovered during the design process. For deep sub-micron integrated circuit designs, antenna violations may occur more often because of thinner gate oxides. Additionally, the fixes may involve moving existing components to make room for the protection diode. The addition of additional components or movement of existing components results in an additional verification step to verify that there are no new timing violations or other layout rule violations introduced by the changes. Because the antenna rule check is generally done toward the end of a design cycle, antenna fixes that require a substantial amount of change to the integrated circuit may adversely impact the design schedule. These additional steps can complicate the design process and may extend the overall design process.
A second conventional approach to the antenna problem tries to reduce the amount of metal connected to the gate of the transistor to bring the antenna ratio below the antenna design rule threshold. This might be done by reducing the size of the interconnect by relocating components such that they are closer together. A smaller interconnect has less metal to accumulate charge during fabrication and is thus less likely to result in a gate voltage potential high enough to blow the gate oxide. Alternatively, the polysilicon and metal interconnections can be isolated from the gate oxide during plasma etching as described in U.S. Pat. No. 5,393,701 issued to Ko et al., dated Feb. 28, 1995.
This second approach may not be feasible in certain situations. For example, many devices in modern integrated circuits have their gates tied to a power grid (Vdd or Vss). The power grid is the power supply network that distributes power to the various components of the integrated circuit. A power plane is generally considered an ideal power distribution network but requires a large amount of metal resources to implement. Thus, a dense power grid may be used in place of a power plane. The entire power grid (Vdd or Vss) generally functions as a giant antenna (metal and vias) during the fabrication process. The power grid typically cannot be changed.
The traditional solutions to on-chip antenna problems described above are generally time consuming and may introduce new design rule errors during the design process. What is needed is a solution to the antenna problem that does not require additional design steps or changes to the existing chip layout. What is further needed is a solution that works for transistors having their gates tied to the power grid.